Sequential Logic, part 2: digital timing charts

Digital timing charts are similar to truth tables but on steroids. They are my absolute favorite for showing how systems should work. As usual, I will reference one of my favorite websites: Automation Direct!

Check out their timing section. When you look at these components, you can get very detailed explanations of what components are and how they function. For instance, try looking at this

cttcountertimertachoverview.pdf

Download PDF • 2.45MB

To describe a simple on delay timer, you can either show this...

Or type this...

With power applied to the CTT, the leading edge of the input signal at START will begin the timing period setting value SV (timing up or down based on parameter (t modE) or by DIP switch 2). At the end of the timing period both outputs will turn ON momentarily for the time set in the output pulse width parameter (tout1) or will be maintained ON if the output pulse width parameter (tout1) is set to 0.00. The trailing edge of the “start” signal has no effect on the outputs or timing period. The leading edge of a “reset” input signal at RST1 will turn OFF the outputs and reset the timing period. The “reset” signal minimum pulse width is set by reset pulse width parameter ( rtSr ) or DIP Switch 8. The leading edge of a “pause” input signal at GATE will pause the timing period after it has been started. The timing period will continue after the trailing edge of the external switch “pause” (Gate) signal. When power is removed, both outputs will turn OFF and the timing period will be reset

Which would you prefer?